1. Field of the Invention
This invention relates generally to peripheral devices, and more particularly provides a high speed bus interface for peripheral devices.
2. Description of the Background Art
Computers would be useless without peripheral devices such as hard disk drives, digital video disks, printers, etc. A peripheral device interface is needed to enable signal communication between a peripheral device and an attached computer. For example, FIG. 1 illustrates a prior art hard disk drive 104, which includes a hard disk drive interface, coupled to a computer 102. The hard disk drive 104 comprises a physical layer 106 which acts as the host interface with the computer 102, and is coupled via a bus 103 (such as an IEEE 1394 bus or a Fiber Channel bus) to the computer 102. The physical layer 106 includes an address decoder 140 for accessing registers in the physical layer.
The hard disk drive 104 further includes a hard disk controller 108, which controls the communication of data between the physical layer 106 and the hard disk 126. The hard disk controller 108 includes a link layer 110, a buffer manager 114 and a disk formatter 116. The link layer 110 performs data packeting services, and is coupled between the physical layer 106 and the buffer manager 114. The buffer manager 114 controls the temporary storage and retrieval of data to and from a data buffer 118 (such as DRAM). The disk formatter 116 performs ID searches and error correction services, and keeps track of available tracks and sectors on the hard disk 126.
The hard disk drive 104 further includes a data channel processor 128, which controls the signal processing operations of the hard disk 126, and is coupled to the disk formatter 116 and to a motion controller 122. As is well known, the hard disk 126 includes a spindle motor (SPM) 142 for controlling disk rotation and a VCM 141 for controlling movement of the hard disk drive actuator arm (not shown). To control the SPM 142, the CPU 120 controls the rotation via the motor driver 124. To control the VCM 141, the motion controller 122 receives offset signals via the data channel processor 128 from the actuator read/write head (not shown). These offset signals indicate the positioning gap between the read/write head and the center of the track.
The data channel processor 128 writes data to the hard disk 126 by transmitting a write signal to the read/write head via a read/write amplifier 143. Similarly, the data channel processor 128 reads data from the hard disk 126 by recognizing the data signal at the actuator read/write head via the read/write amplifier 143. An address decoder 132 in the data channel processor 128 is used to enable access to registers (not shown) in the data channel processor 128. A central processing unit (CPU) 120 is coupled to the hard disk controller 108 elements, to the data channel processor 128 and to the motion controller 122, for enabling the read and write operations between the computer 102 and the hard disk 126.
To maintain efficient flow of operations, dedicated clocks control the frequency of operations of the physical layer 106, of the data channel processor 128 and of the central processing unit 120. That is, a first oscillator (osc1) 134 clocks the frequency of the CPU 120. A second oscillator (OSC2) 136 and divider (1/x) 144 clock the frequency of the physical layer 106. It will be appreciated that the physical layer 106 preferably is clocked to a standard 24.576 MHz frequency. A third oscillator (osc3) 138 and divider (n/m) 130 clock the frequency of the data channel processor 128. It will be further appreciated that the data channel processor frequency is preferably within preset tolerances, which may be based on the speed of the data to be transferred to/from the hard disk 126 and set by the disk drive manufacturer.
Because the physical layer 106 is integrated separately, the hard disk drive 104 is more expensive to manufacture, consumes more power, and occupies more space on a printed circuit board than the system of the present invention described below with reference to the detailed description. Further, integrating the physical layer 106 and link layer 110 together would compromise valuable life cycle of the link layer 110, since the link layer 110 typically lasts longer than the physical layer 106. Still further, because analog and digital circuits must have isolated grounds, it would be difficult to integrate the physical layer 106, which uses mixed digital and analog signals, with the link layer 110 or buffer manager 114. Even further, each of the physical layer 106 and data channel processor 128 needs an oscillator to generate a variable reference clock, which increases cost, compromises power efficiency, makes the circuit layout more complex, and adds additional wires to the printed circuit board. Accordingly, a system and method are needed to reduce circuit cost, power use and occupied printed circuit board space.